The present invention relates to a semiconductor memory device which is very small in size and has a large storage capacity, and more specifically to stacked capacitor (STC) cells of a dynamic random access memory (DRAM) that is adapted to being integrated highly densely.
The integration degree of a DRAM has quadrupled in every three years, and mega-bit memories have already been mass-produced. The degree of integration is heightened by decreasing the sizes of elements. However, reduction in the storage capacity accompanying the decrease in sizes has invited problems with regard to decrease in the signal-to-noise (S/N) ratio, inversion of signals caused by incident alpha particles and maintenance of reliability.
As a memory cell capable of increasing the storage capacity, therefore, a stacked capacitor cell in which part of a storage capacity portion is overlapped on a switching transistor or on an element isolating oxide film disclosed in Japanese Patent Publication No. 55258/ 1986 has been expected to substitute for the existing planar type capacitor.
FIG. 2 is a layout plan view of a conventional STC cell, where reference numeral (2.1) denotes active regions where a channel region and an impurity diffusion layer will be formed to constitute a switching transistor, (2.2) denotes word lines that serve as gate electrodes for the switching transistor, (2.3) denotes contact holes through which the bit lines (2.8) come into contact with the diffusion layer in the substrate, (2.4) denote conductive layers that serve as pads for connecting the bit lines and the diffusion layer together, (2.5) denote contact holes for connecting the lower electrodes (2.6) of storage capacities to the diffusion layer, (2.7) denotes plane electrodes, and (2.8) denotes bit lines.
With the STC cell, the storage capacity portion indicated by the storage capacity lower electrode (2.6) can be extended onto the word line, making it possible to realize a storage capacity which is considerably greater than that of a planar type cell in which only the surface of the substrate is utilized as a storage capacity portion. Therefore, even a small cell area employed for the mega-bit DRAM's is capable of producing a storage capacity which is large enough for operating the circuit. With the conventional planar type cell having the same cell area as the above-mentioned cell, however, it is difficult to obtain a required capacity even if thickness of the insulating film is reduced.
In fact, however, even the STC cell has many problems as will be described below in detail in conjunction with a section view of FIG. 4. The STC cell is fabricated through the below-mentioned steps. First, on a single crystalline semiconductor substrate (4.1) is grown a relatively thick oxide film; (4.2) for electrically isolating the individual elements by the widely known thermal oxidation method. The film thickness ranges from about 100 to about 1000 nm. Then, a gate insulating film (4.3) for forming a switching transistor is grown by the widely known thermal oxidation method. The film thickness decreases with the reduction in the size of element and, usually, ranges from 10 to 50 nm. Polycrystalline silicon containing impurities is deposited and is delineated by the widely known photolithograph method and the dry etching method to form a word line (4.4). Using the delineated word line as a mark, furthermore, impurities having a conductivity type different from that of the substrate (4.1) are introduced by the widely known ion implantation method thereby to form an impurity diffusion layer (4.5). It needs not be pointed out that the heat treatment is necessary for activating the impurity diffusion layer. Then, in order to form a storage capacity portion, polycrystalline silicon (4.7) having the same type of conductivity is deposited by the widely known CVD (chemical vapor deposition) method so as to come into contact with the impurity diffusion layer in the substrate. As will be obvious from the plan view of FIG. 2, the polycrystalline silicon (4.7) is formed also on the word line (4.4) and on the element isolating film (4.2). Therefore, the area of the storage capacity portion increases and, hence, a large storage capacity is maintained.
At this moment, furthermore, polycrystalline silicon is also formed simultaneously even on a place where the contact hole (2.3 in FIG. 2) is formed to connect the bit line (4.11) to the impurity diffusion layer (4.5). Even when the distance among the word lines is small, therefore, the bit line can be connected to the diffusion layer via the polycrystalline silicon layer (2.4 in FIG. 2) without causing the bit line (4.11) and the word line (4.4) to be short-circuited to each other. Here, reference numerals (4.6) and (4.10) denote interlayer insulating films.
In the STC cell of the conventional structure, however pad conductor layer (2.4) must be exposed when a plate electrode (4.9) is to be formed. This is because, the bit line (4.11) and the pad conductor layer must come into contact with each other through this place. In delineating the plate electrode, therefore, a highly sophisticated technology is required to stop the pad conductor layer from being etched accompanying the dry etching of the plate electrode using a very thin capacitor insulating film (4.8) that is formed also on the surface of the pad conductor layer, such that the pad conductor layer will not be ground.
In addition to the above-mentioned problem involved in the production, there exists another essential problem in that it is difficult to decrease the cell area so far as the above-mentioned cell structure is employed. This stems from the fact that a sufficiently large distance must be maintained between the plate electrode (4.9) and the pad conductor layer (2.4) so that the two will not come into contact with each other. It is allowable to omit the pad conductor layer (2.4). In this case, however, the distance among the word lines must be increased to prevent the short-circuiting between the bit lines (4.11) and the word lines (4.4), making it difficult to decrease the cell areas.
With the conventional STC structure as described above, it is difficult to decrease the cell area. Namely, the conventional STC cells are not applicable for very highly integrated DRAM's of 4-mega-bits or greater.
An STC structure free from these problems has been taught in Japanese Utility Model Laid-Open No. 178894/1980. FIG. 3 is a layout plan view of this STC cells. To simplify the drawing, there are shown no lower electrode of storage capacity or plate electrode that are arranged on the contact hole (3.4) in the memory portion.
The feature of this structure resides in that in the active region (3.1), the bit line (3.5) is not arranged on a portion where a contact hole (3.4) of the memory portion is opened. It needs not be pointed out that the bit line (3.5) is in contact with the impurity diffusion layer of the substrate through the contact hole (3.3). The storage capacity portion is formed after the bit lines have been formed. In forming the plate electrodes, therefore, there is no need of exposing the bit line contact portions that are shown in FIGS. 2 and 4. Reference numerals 3.2 denote lead wires.
That is, the plate electrodes need simply cover the memory cell portions.
According to such a cell structure in which the area of the lower electrode of storage capacity is not limited by the delineation of plate electrode, a large storage capacity can be realized yet decreasing the cell area.
Even with this structure, however, great difficulty is involved to shorten the distance among the bit lines if bit lines (3.5) arranged in parallel are not simply overlapped on the contact holes (3.4) of memory portion in the active region (3.1). In the layout of FIG. 3, the distance increases among the bit lines imposing limitation on reducing the cell area. Summary of the Invention
In view of the problems involved in the aforementioned prior art, the object of the present invention is to provide a semiconductor memory device which is small in size and which has a large storage capacity. In particular, the object of the present invention is to provide a semiconductor memory device having fine STC structure that can be used for a highly densely integrated DRAM's of 1-mega-bits or greater.
The semiconductor device referred to in the present invention consists of a switching transistor and a charge storage capacitor as a minimal unit.
FIG. 1 is a plan view illustrating the layout of memory cells according to the present invention. In the present invention, the main portions of active regions (1.1) are in parallel with neither the word lines (1.2) nor the bit lines (1.4) that are at right angles with each other. In order to arrange the active regions most densely according to the present invention, the main portions of active regions are arranged at an angle of 45 degrees with respect to the word lines and the bit lines, and only the portions where the contact holes (1.5) of memory portion are opened are arranged in parallel with the bit lines. Furthermore, the four active regions closest to one active region have extensions of their major portions that meet at right angles with one another. A memory array is constituted by arranging the unit plan layout diagram of FIG. 1 repetitively in the vertical and horizontal directions. Therefore, the peripheral portions of FIG. 1 have been partly omitted.
In FIG. 1, reference numeral 1.3 denotes contact holes for bit lines, 1.6 denotes lower electrodes of storage capacities, and 1.7 denotes plate electrodes.
In this specification, furthermore, the active region stands for all regions of the substrate surrounded by an element isolating insulating film (i.e., a substrate region that is not covered with the element isolating insulating film). Substantially, the active region stands for a region that consists of "a region of impurity diffusion layer in contact with the bit lines", "a region of impurity diffusion layer in contact with the lower electrodes of storage capacities" and "a channel forming portion under the word lines". Further, the main portions of active regions stand for those portions where the channels of switching transistors are formed.
FIG. 5 is a section view illustrating the STC structure according to the present invention. In the present invention, the active regions are aslantly arranged relative to the word lines and bit lines. Therefore, the section view of FIG. 5 is along the line that connects the centers of a pair of contact holes (1.5) of memory portion.
According to the present invention, the active regions simply run in a tilted direction and are formed in a manner that is little different from the conventional forming method.
With the memory cell of the present invention shown in FIG. 1, the word lines (1.2 are tilted with respect to the active regions (1.1) but have their gate lengths determined by the shortest distance between the impurity diffusion layer in contact with the bit lines and the impurity diffusion layer in contact with the lower electrodes of storage capacities.
The word lines (5.4) are insulated by an interlayer insulating film (5.6) from other conductor layers in a self-aligned manner. In this section view, the source and drain have simple structure of impurity diffusion layer. It is, however, also allowable to employ widely known diffusion layers for source and drain with graded impurity profile.
After the word lines are formed, ions are implanted using word lines as a mask in order to form impurity diffusion layers (5.5).
Next, bit lines (5.7) are formed. Like the word lines (5.4), the bit lines (5.7) are insulated using an insulating film (5.8) in a self-aligned manner. In the section view of FIG. 5, bit lines (5.7) exist having the same shape as the pad conductor layers (2.4) of FIG. 4.
With a lattice being constituted by the word lines and bit lines as described above, the surfaces are represented by a pair of diffusion layers in which the active regions (1.1) have been formed already in the valleys among the word lines and bit lines as is clear from the layout plan view of FIG. 1. Lower electrodes (1.6 and 5.9) of storage capacities are formed thereon. The lower electrodes are then delineated to form a capacitor insulating film (5.10), and a plate electrode (5.11) is formed thereon. The plate electrode (5.11) needs not be delineated on the memory array unlike the case of STC cells shown in FIGS. 2 and 4. Reference numeral (5.12) denotes an interlayer insulating film on the plate electrode (5.11) on which aluminum wirings (not shown) will be formed.
In FIG. 5, reference numeral 5.1 denotes a semiconductor substrate, 5.2 denotes an element isolating insulating film, 5.3 denotes a gate insulating film, and 5.8 denotes an interlayer insulating film.
The element isolating film (5.2) is formed on the surface of the single crystalline semiconductor substrate (5.1) other than the active regions.
The lower electrode (5.9) of storage capacity is composed of a refractory metal such as tungsten or polycrystalline silicon and has a thickness of usually from 100 to 500 nm by taking the steps in thickness into consideration. However, the thickness needs not be limited thereto only; e.g., the lower electrode (5.9) may have a large thickness as far as there does not develop any problem in regard to the steps in thicknesses.
Examples of the material of the capacitor insulating film (5.10) include silicon oxide film, silicon nitride film, a composite film consisting of silicon oxide film and silicon nitride film, and refractory metal oxide films such as Ta.sub.2 O.sub.5, as well as a composite film of refractory metal oxide film and silicon oxide film and a composite film of refractory metal oxide film and silicon nitride film. The capacitor insulating film may have a thickness nearly equal to that of the conventional STC cells.
The material of the plate electrode (5.11) may be polycrystalline silicon or a refractory metal such as tungsten. The film thickness thereof may be nearly the same as that of the conventional STC cells.
The width and pitch of the word lines (5.4) and bit lines (5.7) are determined by the cell area. In the case of 16 mega-bits, for instance, the word lines have a width of 0.5 to 0.7 .mu.m and a pitch of 1 to 1.4 .mu.m, and the bit lines have a width of 0.6 to 0.9 .mu.m and a pitch of 1.2 to 1.8 .mu.m.
With the shape and arrangement of active regions being selected as described above, there exists no constraint on layout among the bit lines (3.5) that took place in the case of the traditional structure, and the pitch among the bit lines can be greatly decreased. That is, in the conventional structure, the bit lines (3.5) pass through one side only of the contact holes (3.4) of memory portion. According to the present invention, on the other hand, the contact hole (1.5) of memory portion is sandwiched between the two bit lines (1.4).
As described earlier, furthermore, both the word lines (1.2) and the bit lines (1.4) are insulated from other conductor layers in a self-aligned manner, making it possible to shorten the pitch among the word lines as well as to open, in a self-aligned manner, the contact holes (1.5) of memory portion through which the storage capacity portions, i.e., lower electrodes (1.6 and 5.9) of storage capacities come into contact with the substrate.
By adapting the above-mentioned structure, a memory cell having a very small area can be constituted as shown in FIG. 1 to realize a very highly integrated DRAM's of greater than 4 mega-bits.
In addition, unlike the conventional STC structure shown in FIG. 2, the lower electrodes (1.6 and 5.9) of storage capacities are not limited for their areas by the delineation of the plate electrodes (1.7 and 5.11) formed thereon, and can be uniformly arranged maintaining a minimum delineating space, With the STC structure of the present invention, furthermore, the bit lines are completely covered by the plate electrodes having a fixed potential and by the conductor layers of storage capacity portions. Therefore, the interline capacitance among the bit lines decreases greatly, and memory array noise decreases, i.e., coupling noise stemming from the interline capacitance decreases compared with that of the conventional structure.